Conventional memory devices are frequently organized to store a plurality of bits of related data in adjacent memory cells that are electrically coupled to a common word line. These memory devices may also include address decoding logic, which can access the common word line during writing and reading operations and thereby direct write data to or read data from a group of the adjacent memory cells. Such conventional decoding logic frequently requires that a plurality of data bits be routed from a corresponding number of bond pads scattered around a periphery of an integrated circuit chip to memory cells associated with a respective word line. These routing operations frequently establish relatively large and nonuniform interconnect paths associated with each of the plurality of data bits being written to or read from an addressed location in the memory device.
Techniques have been developed to limit the degree of nonuniformity of interconnect paths within memory devices. Such techniques include dividing a core of memory cells within a memory device into quadrants, with each quadrant being configured to communicate with a corresponding group of bond pads. Each quadrant may also have independent addressing logic. Other techniques, such as those disclosed in U.S. Pat. No. 6,396,766 to Lee, include using multiplexer logic to reduce the differences between the shortest and longest interconnect paths within a multi-bank memory device.
Notwithstanding these conventional techniques, there continues to be a need for multi-bank memory devices having even faster memory access timing characteristics.